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ATI R5xxx Roadmap Inside: Value First


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http://www.anandtech.com/video/showdoc.aspx?i=2501

 

RV530

 

600MHz Core Clock

1400MHz Memory Clock

512MB Maximum Memory for "XT"

256MB Maximum Memory for "Pro"

128-bit Memory

12 Pipelines

Maximum 16x32MB 1.4ns GDDR3

RV515 also comes in two separate versions: a "Pro" and an "LE" version. Again there will be AGP versions much after the launch in the form of Rialto bridged cards. ATI roadmaps do not indicate there will be CrossFire versions of RV515.

 

RV515

 

450MHz Core Clock

800MHz Memory Clock

256MB Maximum Memory Support

128-bit Memory

4 Pipelines

Maximum 16x16MB 2.5ns GDDR2

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Ja! ;) Blir spennende å se om nvidia trenger å lansere 7800 Ultra da!

 

Ser iallefall bra ut at "R520"XL kommer i september..

"R520"XT skal komme i oktober står det. Det samme gjelder CrossFire-utgaven til R520.

 

Synes det er merkelig at R520 også krever et spessielt "Master kort" for å bruke CrossFire, men det kan vel tyde på at R520 var for "ferdig" når ATi bestemte seg for hvordan de skulle implementere Crossfire, slik at de ikke fikk lagt til noen ekstra funksjoner i brikken...

 

Oddly enough, ATI is going with a dual-slot configuraton for the high end R520s. Even though the card will physically only occupy a single PEG, the thermals are so massive that they take up two expansion slots, as with the X850XT cards today.

Høres på meg ut som om dette blir varmt...

 

Edit: skrivefil....

Endret av [GDI]Raptor
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Ja!  ;) Blir spennende å se om nvidia trenger å lansere 7800 Ultra da!

Blir spennende å se om det vil være nok.. Men dem burde nok heller være beskymret over R580.

 

Synes det er merkelig at R520 også krever et spessielt "Master kort" for å bruke CrossFire, men det kan vel tyde på at R520 var for "ferdig" når ATi bestemte seg for hvordan de skulle implementere Crossfire, slik at de ikke fikk lagt til noen ekstra funksjoner i brikken...

Eller så er det mulig dem forventer at crossfire ikke vil bli utbredt nok til at det er hensiktmessig å implentere dette på alle kortene.

Endret av MistaPi
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Vet ikke hvor mye man skal tro på dette men poster en link jeg kom over på Rage3d.

 

ATI R520 is expected to be released in September and will be built on a 90nm process. The R520 core is expected to based on an entirely new core design featuring SM3 (and above), GDDR4 memory support for memory speeds of 1.2Ghz+ and built in H.264 hardware decode assistance - the encoding standard for both BluRay and HD-DVD. H.264 decoding requires significant processing - a 3.6Ghz P4 runs at around 90 - 95% CPU usage without acceleration, compared to around 33% with R520 GPU acceleration. The architecture of the R520 is expected to contain separate pixel and vertex shaders (unlike the R500 core designed for the X-Box 360 which has unified shaders) with an expected 24+ pixel pipelines (possibly 24 to compete with the 7800GTX and 32 to compete with a theoretical 7800 Ultra) and up to 10 vertex shaders running at a clock speed of around 600Mhz. The core of R520 is expected to contain well over 300 million transistors and will be available exclusively on PCI Express in conjunction with 512MB of memory. It is expected to retain at over $600 upon release.

 

http://freespace.virgin.net/m.warner/RoadmapQ305.htm

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GDDR4 memory support for memory speeds of 1.2Ghz+

Etter hva jeg har ført så bruker den ikke GDDR4 minne, men GDDR3

 

built in H.264 hardware decode assistance - the encoding standard for both BluRay and HD-DVD. H.264 decoding requires significant processing

Dette kommer iallefall også for GeForce 7-serien i 80-serien av nVidia ForceWare

 

expected 24+ pixel pipelines (possibly 24 to compete with the 7800GTX and 32 to compete with a theoretical 7800 Ultra) and up to 10 vertex shaders running at a clock speed of around 600Mhz

På Beyond3D er det vel ganske stor enighet om at R520 får 16 pipelines

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My guess based on some facts and other guesses: :D

 

RV530: 4-1-3-2 = ROPs / ? / pipelines or ALUs per ROP / Z, Stencil

 

RV530 is 12-pipelines chip and it is too small for 256bit memory bus. So 12 or 8 ROPs would be useless with 128bit MB (more tranzistors, higher price, higher possibility of some defect...). But 4 ROPs would be limitation for Z/Stencill operations, so 4 "extreme" ROPs were used (2x Z/Stencil) like a compensation. It is possible, that R5xx ROPs are able to do 4x MSAA, so 4 ROPs combined with +-600MHz clock speed wouldn't be sacrificing even when using AA.

 

R520... 16-1-1-1

 

version a) 16 ROPs, 16 pipelines with ? ALUs, (chip would be similar to other RV5x0 architecture)

version b) 16 ROPs, 16 "extreme" ALUs, (chip would be similar to other RV5x0 architecture)

 

R580... 16-1-3-1

 

version a) 16ROPs, 48 simple pipelines, 1 ALU per pipeline

version b) 16ROPs, 48 ALUs, a bit similar to Xenos architecture, but w/o US

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