Mushkin minne, bra?

[Energi]

Har noen vært borti Mushkin minne?

Så noen heromdagen, de så rimelig frekke ut.

 

Her er de:

 

http://www.mushkin.com/epages/Mushkin.stor...uct/View/991095

 

Lekkert utseende, svart PCB og 2-2-2@433MHz!

Tight timings?

 

Regner med ingen i Norge forhandler disse, noen som vet?

[DrErling]

Mushkin er topnotch og har såvidt jeg vet aldri laget dårlig minne. De er på topp innimellom mht ytelse også.

 

DrErling

[venomzorg]

2-2-2 @ 433MHz ?

 

 

står det på sia der

[venomzorg]

åja, man kunne trykke på den ?'n.

 

 

 

 

 

1T, tRAS and CMD (short for Command) rate, are somewhat complicated and more difficult to understand than simple access and precharge latencies (the first three specs). We find the level of misinformation on tRAS and CMD rate somewhat alarming especially when used to create a false concept of performance by unscrupulous memory vendors.

 

What is CMD rate and why is it misunderstood?

 

CMD rate is generally used to describe the time from a chip select until a row activate command can be given. The chip select defines the physical bank in which the row is located. In a system running a single, single sided memory module, there is never a question which bank will be selected since there is only one. Keep that in mind when reading the small print somewhere stating that the 1T CMD rate only applies to a single module in the system.  

 

More generally, the CMD Rate is a chipset latency that is not determined by the memory but by the time it takes the chipset to translate the virtual address space into physical memory addresses. Needless to say that higher density system memory with its more addresses will take longer to decode than a single low density module, even if it is double sided. Also keep in mind that the logical true for any signal on the command bus is a low voltage. Now, increasing the voltage is often enough simple enough, all you need to do is inject enough current. Dropping the voltage again, especially in an interconnected network may occur somewhat more slowly, especially if it is only one line out of 6 that needs to drop.  

 

Intel has taken care of this problem by simply limiting the number of banks supported per memory channel to four. This, in turn allows them to run all their chipsets on a fixed CMD rate of 1T, regardless of how much memory is installed in the system. Keep in mind that vendors that qualify only certain modules with a CMD rate of 1T may experience severe stability issues on modules that are not specifically covered under their 1T assurance umbrella.  

 

Currently, the only chipset manufacturers that are even condoning a 2T CMD rate are VIA technologies (mostly for the sake of supporting registered DIMMs) and SIS (on some of their chipsets that allowed asynchronous, overclocked operation of DRAM)

 

Overall, rating a module as 1T is either false advertising or needs to be excused as blatant ignorance as all unbuffered modules are capable of a 1T CMD rate up to four banks per channel, beyond which chipset limitations come into play.

 

 

What is tRAS and why is it backwards and important at the same time?

 

The word latencies is generally used to describe a delay. However, Merriam-Webster defines the word’s origin as period of dormancy and in technical parlance, latency is often used to describe simply the duration of any event. One example is the PCI latency which describes the time any device has access to the PCI bus before it will be automatically disconnected to allow other devices access to the same resources.  

 

Why are we talking about this? Very simple, the access latencies of any device to the PCI bus are usually eight cycles, but the total latency can be set from 16-256 cycles. This shows that the same word is used to describe two entirely different parameters, the first being the time until any transactions can start, the second referring to the time that is available for transactions (minus the access latencies). As an example, a PCI latency of 32 will carry a penalty (access latency) of 8 cycles which leaves 24 cycles for actual data transfers. Therefore, decreasing this latency will not increase performance, on the contrary.  

 

The exact same is true for tRAS short for the RAS Pulse width. Historically, tRAS was defined as the time needed to establish the necessary potential between a bitline pair within the memory array until it was safe to write back the data to the memory cells of origin after a (destructive) read. Pay attention to the word read here.  

 

Memory, in many ways is like a book, you can only read after opening a book to a certain page and paragraph within that particular page. The RAS Pulse Width is the time until a page can be closed again. Therefore, just by definition, the minimum tRAS must be the RAS-to-CAS delay plus the read latency (CAS delay). That is fine for FPM and EDO memory with their single word data transfers. With SDRAM, memory controllers started to output a chain of four consecutive quadwords on every access. With DDR, that number has increased to eight quadwords that effectively are two consecutive bursts of four.  

 

Now imagine someone closes the book you are reading from in the middle of a sentence. Right in your face! And does it over and again. This is what happens if tRAS is set too short. So here is the really simple calculation: The second burst of four has at least to be initiated and prefetched into the output buffers (like you get a glimpse at the headline in a book) before you can close the page without losing all information. That means that the minimum tRAS would be tRCD+CAS latency + 2 cycles (to output the first burst of four and make way for the second burst in the output buffers).

 

Any tRAS setting lower tRCD + CAS + 2 cycles will allow the memory controller to close the page “in your face!” over and again and that will cause a performance hit because of a truncated transfer that needs to be repeated. Along with those hassles comes the self-explanatory risk for data corruption. That one is not a real problem as long as the system is kept running but in case it is shut down and the memory content is written back to the hard disk drive, the consequences can be catastrophic. For the drive, that is.  

 

What does this spec mean?

 

Take for example 2.5-4-4 as the latency rating for a module. Latency is a measure of delay, that means the 2.5 rating in 2.5-4-4 indicates a 2.5 clock cycle delay. And the 4 ratings mean a 4 clock cycle delay. The clock cycle delays that these ratings are measuring is what determine how long it takes your CPU to write or remove data from memory. So the lower these latencies are, the less time your CPU spends idle waiting for data which results in higher performance.

 

The position of the rating in 2.5-4-4 determines what latency the rating is referring to. The ratings, in order, represent the latency ratings for CAS, tRCD (RAS-to-CAS delay), and tRP (RAS Precharge). It would take a long time to explain what each of these latency ratings means, so to make a long story short the lower the latency the higher the performance of your CPU.

 

Why does company X have memory modules that are rated for faster speed and/or lower latencies than Mushkin?

 

We make sure that all our modules run at the specified speed rating and above by a substantial margin. Many companies just meet the specs under optimal conditions, for instance with only one module installed. Keep in mind when looking at module ratings whether the company selling them rates them according to their abilities under heavy load on various chipsets. Meaning that these ratings need to represent what the module is capable of when installed with all the DIMM slots in various motherboards filled, which is what we do. Unscrupulous or naive memory resellers on the Internet will rate their modules by what they're capable of when running by themselves and on certain chipsets. Memory modules are generally capable of faster speeds and lower latencies when only one module is installed and on certain chipsets. So while it may look like their memory is faster than ours, in actuality they just came up with their ratings from ideal conditions that aren't representative of all real world scenarios. So their memory isn't necessarily better than ours, they just have lower standards for rating their modules. Companies like this will also have misleading tech support (i.e. It's your fault, not ours when the modules won't run as rated), and poor refund policies with hefty restocking fees when you want to return a module.